Copper has become widely adopted to form multilevel interconnects required in today's ultra large scale integration (ULSI) semiconductor devices, due to its lower resistivity compared to aluminum and its improved electromigration resistance.
Multilevel interconnects consist in a network of copper lines (formed into trenches) that are used to distribute various signals as well as power and ground to different areas of an integrated circuit. In order to improve real estate-efficiency, these lines are stacked in several levels separated by a dielectric material and these levels are connected to each other through vertical apertures called vias.
Lines and vias are usually formed using the damascene process sequence (See for example S. Wolf: “Silicon processing for the VLSI Era”, Vol. 4, p. 671-687) in which, at each level of the interconnect system, features are etched in the dielectric material and subsequently filled with copper before being planarized. A simplified version of this sequence can be described as follows:                dry etching of the dielectric material to form trenches and/or vias;        deposition (conventionally by physical vapor deposition—PVD) of a Cu diffusion barrier (usually TaN/Ta) since copper is a fast diffuser through dielectrics and can reach the underlying transistors built into the silicon, causing device failures;        deposition of a “seed layer” of copper, conventionally by PVD;        electrochemical deposition of copper to fill the vias and trenches;        planarization by chemical-mechanical polishing (CMP) to leave inlaid copper lines; that is, the surface of copper at the same level as the surface of the surrounding dielectric;        deposition over the inlaid copper lines of a dielectric encapsulation layer (generally SiCN, SiN, SiC, SiOCN or SiON deposited by plasma-enhanced chemical vapor deposition—PECVD) which serves as a copper diffusion barrier as well as an etch-stop layer (ESL) during patterning and etching of the overlying inter-metal dielectric material;        deposition of the next level of inter-metal dielectric material (generally a material having a low dielectric permittivity, below 4.0).        
As device integration density increases, the width of lines, vias and other features on the circuits decreases. As a result, the cross-section of lines and vias decreases and current densities carried through copper lines increase.
The increase in current density enhances the electromigration phenomenon in copper interconnects. Electromigration can be described by the displacement of metal atoms in interconnect lines in the direction of the current flow.
As a result of the motion of copper atoms, vacancies and then voids are formed in certain areas of copper lines, causing reliability issues and, with time, complete failures of the interconnect system and subsequently of the integrated circuit itself.
It has been shown (See for example C. K. Hu et al., Microelectronics and Reliability, Vol. 46, Issues 2-4, p. 213-231) that in copper lines, electromigration primarily proceeds through surface diffusion of copper atoms or ions as the surface diffusion coefficient of copper is higher than its self-diffusion coefficient. Surface diffusion of copper occurs preferentially along the weakest interface of a copper line where loosely bound copper atoms have more mobility.
In copper lines, the weakest interface is the top surface of the line in contact with the ESL (See for example T. C. Wang et al., Thin Solid Films, 498 (2006) p. 36-42).
It is therefore desirable to enhance the adhesion strength between copper and the ESL in order to limit surface diffusion of copper, improve electromigration resistance and reliability of the interconnect system.
Several techniques have been proposed to achieve better adhesion of ESL to copper and better electromigration resistance.
Plasma treatments in reducing atmosphere such as ammonia or hydrogen have been employed (see for example U.S. Pat. Nos. 6,946,401, 6,764,952 and 6,593,660) to reduce copper oxides and eliminate other contaminants present on the copper surface, thus resulting in better adhesion of the ESL. However, the physical and directional nature of the treatment induces some copper sputtering over the surrounding dielectric areas resulting in a risk of higher line-to-line leakage. Some of the top surface copper is removed during the process, resulting in increased line resistance which decreases the interconnect performance.
Silicidation of the copper surface has been proposed to enhance adhesion with Si-based ESL (see for example U.S. Pat. Nos. 6,492,266, 6,977,218 and 5,447,887). During the silicidation process, some copper from the line is consumed to form the more resistive copper silicide. This results in increased line resistance also.
Doping copper with other metals such as Ag or Zr, either in the bulk of the line during the electrochemical filling step, or in a localized manner on the top surface of copper lines has also been suggested to enhance resistance to electromigration (see for example U.S. Pat. Nos. 6,387,806 and 6,268,291). In this case, the dopants will act either as physical copper diffusion blockers or will assist in creating larger copper grains to eliminate copper diffusion pathways.
Once again, the use of dopants which have lower electrical conductivity compared to copper will increase line resistance.
The use of selective and conductive capping layers over copper lines such as CoWP layers deposited by an electroless deposition process has also been proposed (see for example U.S. Pat. Nos. 6,893,959 and 6,902,605 and US application No. 2005/0266673). In this case, copper surface diffusion is limited by metal-to-metal bonding. Such capping layers may also possess copper diffusion barrier properties, thus theoretically eliminating the need for a SiCN layer.
However, their integration in the dual damascene process sequence without the use of ESLs is not straightforward; in particular when via misalignments have to be taken into account.
Furthermore, deposition selectivity is very difficult to maintain when line density increases. This causes increased line-to-line leakage and, in some cases, creates line-to-line shorts.
In order to improve the reliability of ULSI devices by increasing interconnect electromigration resistance and to alleviate the aforementioned limitations of the prior art, there is a clear need of a method which can (1) limit or eliminate top surface diffusion of copper atoms or ions in copper lines, (2) improve the copper/ESL interface by enhancing its adhesion strength and electromigration resistance, (3) preserve the electrical characteristics of the interconnect system, in particular line resistance and line-to-line leakage.